14-Bit Registered Buffer With SSTL_2 Inputs And Outputs

This 14-bit registered Buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.
The SN74SSTVF16857 operates from a differential Clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, Clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all Registers are reset, and all outputs are forced low. The LVCMOS RESET input always must be held at a valid Logic high or low level.
To ensure defined outputs from the Register before a stable Clock has been supplied, RESET must be held in the low state during power up.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
SN74SSTVF16857VRG4 Texas Instruments 14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TVSOP 0 to 70
SN74SSTVF16857GR Texas Instruments 14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TSSOP 0 to 70
SN74SSTVF16857GRG4 Texas Instruments 14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TSSOP 0 to 70
SN74SSTVF16857VR Texas Instruments 14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TVSOP 0 to 70
SN74SSTVF16857 's PackagesSN74SSTVF16857 's pdf datasheet
SN74SSTVF16857GR TSSOP
SN74SSTVF16857GRG4 TSSOP
SN74SSTVF16857VR TVSOP
SN74SSTVF16857VRG4 TVSOP




SN74SSTVF16857 Pinout, Pinouts
SN74SSTVF16857 pinout,Pin out
This is one package pinout of SN74SSTVF16857,If you need more pinouts please download SN74SSTVF16857's pdf datasheet.

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