4096 X 18 Synchronous FIFO Memory
The SN74V215 SN74V225 SN74V235 and SN74V245 are very high-speed, low-power CMOS clocked first-in first-out (FIFO) Memories They support Clock frequencies up to 133 MHz and have read-access times as fast as 5 ns. These DSP-Sync? FIFO Memories feature read and write controls for use in applications such as DSP-to-processor Communication DSP-to-analog front end (AFE) buffering, network, Video and data Communications
These are synchronous FIFOs which means each port employs a synchronous Interface All data transfers through a port are gated to the low-to-high transition of a continuous (free-running) port Clock by enable signals. The continuous Clocks for each port are independent of one another and CAN be asynchronous or coincident. The enables for each port are arranged to provide a simple Interface between DSPs Microprocessors and/or buses controlled by a synchronous Interface An output-enable (OE) input controls the 3-state output.
The synchronous FIFOs have two fixed flags, empty flag/output ready (EF/OR) and full flag/input ready (FF/IR), and two programmable flags, almost-empty (PAE) and almost-full (PAF). The offset loading of the programmable flags is controlled by a simple state machine, and is initiated by asserting the load pin (LD). A half-full flag (HF) is available when the FIFO is used in a single-device configuration.
Two Timing modes of operation are possible with these devices: first-word fall-through (FWFT) mode and standard mode.
In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A read enable (REN) does not have to be asserted for accessing the first word.
In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.
These devices are depth expandable, using a daisy-chain technique or FWFT mode. The XI and XO pins are used to expand the FIFOs In depth-expansion configuration, first load (FL) is grounded on the first device and set to high for all other devices in the daisy chain.
The SN74V215 SN74V225 SN74V235 and SN74V245 are characterized for operation from 0C to 70C.
By Texas Instruments
|SN74V245-20PAG||Texas Instruments||4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70|
|SN74V245-7PAG||Texas Instruments||4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70|
|SN74V245-10PAG||Texas Instruments||4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70|
|SN74V245-15PAG||Texas Instruments||4096 x 18 Synchronous FIFO Memory 64-TQFP 0 to 70|
|SN74V245-15PAGEP||Texas Instruments||Enhanced Product 4096 x 18 Synchronous FIFO Memory 64-TQFP -55 to 125|
|V62/13606-01XE||Texas Instruments||Enhanced Product 4096 x 18 Synchronous FIFO Memory 64-TQFP -55 to 125|
|SN74V245 Pb-Free||SN74V245 Cross Reference||SN74V245 Schematic||SN74V245 Distributor|
|SN74V245 Application Notes||SN74V245 RoHS||SN74V245 Circuits||SN74V245 footprint|