DUAL J-NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

The HC112 devices contain two independent J-K negative-edge-triggered Flip-Flops A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup time requirements are transferred to the outputs on the negative-going edge of the Clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the fall time of the CLK pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile Flip-Flops perform as toggle Flip-Flops by tying J and K high. By Texas Instruments
Part Manufacturer Description Datasheet Samples
SNJ54HC112W Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CFP -55 to 125
SNJ54HC112J Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 16-CDIP -55 to 125
SNJ54HC112FK Texas Instruments Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset 20-LCCC -55 to 125
SNJ54HC112 's PackagesSNJ54HC112 's pdf datasheet
SN54HC112J DIP
SNJ54HC112FK LCCC
SNJ54HC112J DIP
SNJ54HC112W CFP




SNJ54HC112 Pinout, Pinouts
SNJ54HC112 pinout,Pin out
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