SSTU32864 1.8 V Configurable Registered Buffer For DDR2 RDIMM Applications

The SSTU32864 is a 25-bit 1:1 or 14-bit 1:2 configurable registered Buffer designed for 1.7 V to 1.9 V VDD operation. All Clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The SSTU32864 operates from a differential Clock (CK and CK). Data are registered at the crossing of CK going HIGH, and CK going LOW. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1:1 (when LOW) to 14-bit 1:2 (when HIGH). The device supports low-power standby operation. When the reset input (RESET) is LOW, the differential input receivers are disabled, and undriven (floating) data, Clock and reference voltage (VREF ) inputs are allowed. In addition, when RESET is LOW all Registers are reset, and all outputs are forced LOW. The LVCMOS RESET and Cn inputs must always be held at a valid Logic HIGH or LOW level. To ensure defined outputs from the Register before a stable Clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CK and CK. Therefore, no Timing relationship CAN be guaranteed between the two. When entering reset, the Register will be cleared and the data outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the Register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the Clock is stable during the time from the LOW-to-HIGH transition of RESET until the input receivers are fully enabled, the design of the SSTU32864 must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will Gate the Qn outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs LOW. If the DCS-control functionality is not desired, then the CSR input CAN be hardwired to ground, in which case the setup time requirement for DCS would be the same as for the other Dn data inputs. The SSTU32864 is available in a 96-ball, low profile fine-pitch ball grid array (LFBGA96) package.
By NXP Semiconductors
Part Manufacturer Description Datasheet Samples
SSTU32864AHLF Integrated Device Technology Inc CABGA-96, Tray
SSTU32864AHLFT Integrated Device Technology Inc CABGA-96, Reel
SN74SSTU32864DZKER Texas Instruments 25-Bit Configurable Registered Buffer With SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTU32864DGKER Texas Instruments 25-Bit Configurable Registered Buffer With SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTU32864EZKER Texas Instruments IC SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, GREEN, PLASTIC, LFBGA-96, FF/Latch
SN74SSTU32864CGKER Texas Instruments SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96, PLASTIC, LFBGA-96
SN74SSTU32864ZKER Texas Instruments 25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTU32864GKER Texas Instruments 25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
SN74SSTU32864CZKER Texas Instruments 25-Bit Configurable Registered Buffer with SSTL_18 Inputs and Outputs 96-LFBGA 0 to 70
74SSTU32864DBFG Integrated Device Technology Inc CABGA-96, Tray
SSTU32864 's PackagesSSTU32864 's pdf datasheet
SSTU32864EC LFBGA
SSTU32864EC-G LFBGA




SSTU32864 Pinout, Pinouts
SSTU32864 pinout,Pin out
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