SSTUG32865 1.8 V 28-bit 1 : 2 Registered Buffer With Parity For DDR2-1G RDIMM Applications

The SSTUG32865 is a 1.8 V 28-bit 1 : 2 Register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 Register but integrates the functionality of the normally required two Registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs. The SSTUG32865 also integrates a parity function, which accepts a parity bit from the Memory controller compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). It further offers added features over the JEDEC standard Register in that it CAN be configured for normal or high output drive strength, simply by tying input pin SELDR either HIGH of LOW as needed. This allows use in different module designs varying from low to high density designs by picking the appropriate drive strength to match net loading conditions. Furthermore, the SSTUG32865 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard Register The SSTUG32865 is packaged in a 160-ball, 12 x 18 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which, while requiring a minimum 9 mm x 13 mm of board space, allows for adequate signal routing and escape using conventional card technology.
By NXP Semiconductors
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SSTUG32865ET-G TFBGA
SSTUG32865ET-S TFBGA




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