SSTUG32868 1.8 V 28-bit 1 : 2 Configurable Registered Buffer With Parity For DDR2-1G RDIMM Applications

The SSTUG32868 is a 1.8 V 28-bit 1 : 2 Register specifically designed for use on two rank by four (2R x 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 Register but integrates the functionality of the normally required two Registers in a single package, thereby freeing up board real-estate and facilitating routing to accommodate high-density Dual In-line Memory Module (DIMM) designs. The SSTUG32868 also integrates a parity function, which accepts a parity bit from the Memory controller compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). It further offers added features over the JEDEC standard Register in that it is permanently configured for high output drive strength. This allows use in high density designs with heavier than normal net loading conditions. Furthermore, the SSTUG32868 features two additional chip select inputs, which allow more versatile enabling and disabling in densely populated memory modules. Both added features (drive strength and chip selects) are fully backward compatible to the JEDEC standard Register Finally, the SSTUG32868 is optimized for the fastest propagation delay in the SSTU family of Registers The SSTUG32868 is packaged in a 176-ball, 8 x 22 grid, 0.65 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 6 mm x 15 mm of board space) allows for adequate signal routing and escape using conventional card technology.
By NXP Semiconductors
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SSTUG32868ET-G TFBGA
SSTUG32868ET-S TFBGA




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