SSTUP32866 1.8 V 25-bit 1 : 1 Or 14-bit 1 : 2 Configurable Registered Buffer With Parity And Programmable Output For DDR2-800 RDIMMs

The SSTUP32866 is a 1.8 V configurable Register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 and SSTUB32866 registered Buffers The Register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration CAN be designated as Register A or Register B on the DIMM. It offers added features over the JEDEC standard Register in that it CAN be configured for high or normal output drive strength, as well as for operation to 667 MT/s or 800 MT/s, simply by tying two input pins HIGH or LOW as needed. The SSTUP32866 accepts a parity bit from the Memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The SSTUP32866 is packaged in a 96-ball, 6 x 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm x 5.5 mm).
By NXP Semiconductors
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SSTUP32866EC-G LFBGA




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