64 Kbit Serial I2c Bus Eeprom With Hardware Write Control On Top Quarter Of Memory

These devices M34D64 are compatible with the I2C memory protocol. This is a two wire serial Interface that uses a bi-directional data bus and serial Clock The devices carry a built-in 4-bit Device Type Identifier code (1010) in accordance with the I 2C bus definition. The device behaves as a slave in the I 2C protocol, with all memory operations synchronized by the serial Clock Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a Device Select Code and RW bit (as described in Table 2), terminated by an acknowledge bit. When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus masters 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read. By STMicroelectronics
M34D64 's PackagesM34D64 's pdf datasheet

M34D64 Pinout, Pinouts
M34D64 pinout,Pin out
This is one package pinout of M34D64,If you need more pinouts please download M34D64's pdf datasheet.

M34D64 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

M34D64 Pb-Free M34D64 Cross Reference M34D64 Schematic M34D64 Distributor
M34D64 Application Notes M34D64 RoHS M34D64 Circuits M34D64 footprint
Hot categories