SY10E167 SY100E167 SY10E167 SY100E167 6-BIT 2:1 MUX-REGISTER

The SY10E167 SY100E167 SY10E167 SY100E167 offer six 2:1 multiplexers followed by D Flip-Flops with single-ended outputs, designed for use in new, high-performance ECL systems. The Select (SEL) control allows one of the two data inputs to the multiplexer to pass through. The two external Clock signals (CLK1, CLK2) are gated through a logical OR operation before use as control for the six Flip-Flops The selected data are transferred to the Flip-Flops on the rising edge of CLK1 or CLK2 (or both). By Micrel Semiconductor
SY100E167 's PackagesSY100E167 's pdf datasheet
SY10E167JC
SY10E167JCTR
SY100E167JC
SY100E167JCTR




SY100E167 Pinout, Pinouts
SY100E167 pinout,Pin out
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