CLOCK GENERATION CHIP

The SY100S834 SY100S834L is low skew (1, 2, 4) or (2, 4, 8) Clock generation chip designed explicitly for low skew Clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices CAN be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source CAN be AC-coupled into the device. If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the SY100S834/L under single-ended input conditions. As a result, this pin CAN only source/sink up to 0.5mA of current. By Micrel Semiconductor
SY100S834L 's PackagesSY100S834L 's pdf datasheet
SY100S834




SY100S834L Pinout, Pinouts
SY100S834L pinout,Pin out
This is one package pinout of SY100S834L,If you need more pinouts please download SY100S834L's pdf datasheet.

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