SY100S891 5-BIT REGISTERED TRANSCEIVERThe SY100S891 is a 5-bit registered transceiver
containing five Bus Transceivers with both transmit and
receive Registers The bus outputs (BUS0 BU4) are
specified for driving a 25 ohm bus and the receive outputs
(Q0 4) are specified for driving a 50 ohm line. The
bus outputs have a normal high level output voltage and
a normal low level output voltage when the bus enable
(BUSEN0 BUSE4) is high. However, the output is
switched to a cut-off level when a bus-enable is low.
This cut-off level is sufficiently low that a relatively high
impedance is presented to the bus in order to minimize
reflections. There is one bus-enable for each bus driver;
a Clock (CLK1) which is common to all five bus driver
registers; and a separate Clock (CLK2) which is common
to all five receive Registers Data at the D inputs is clocked
to the Bus Register by a positive transition of CLK1 and
data on the bus is clocked into the Receiver Register by
a positive transition of CLK2. A high on the Master Reset
clears all Registers By Micrel Semiconductor
|
|
SY100S891 Pb-Free | SY100S891 Cross Reference | SY100S891 Schematic | SY100S891 Distributor |
SY100S891 Application Notes | SY100S891 RoHS | SY100S891 Circuits | SY100S891 footprint |