SY89872U 2.5V, 2GHz Any Diff. In-to-LVDS Programmable Clock Divider/Fanout Buffer With Internal Termination

This 2.5V low-skew, low-jitter, precision LVDs output Clock divider accepts any high-speed differential Clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDs and divides down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input Clock The SY89872U includes two output banks. Bank A is an exact copy of the input Clock (pass through) with matched propagation delay to Bank B, the divided output bank. Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz Clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary Clock components. By Micrel Semiconductor
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SY89872U Pinout, Pinouts
SY89872U pinout,Pin out
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