SY89874U 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider/Fanout Buffer With Internal Termination

This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDs or HSTL Clock input signal and dividing down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input Clock Available divider ratios are 2, 4, 8 and 16, or straight pass-through. In a typical 622MHz Clock system this would provide availability of 311MHz, 155MHz, 77MHz or 38MHz auxiliary Clock components. By Micrel Semiconductor
SY89874U 's PackagesSY89874U 's pdf datasheet
SY89874UMI MLF
SY89874UMITR MLF
SY89874UMG MLF
SY89874UMGTR MLF




SY89874U Pinout, Pinouts
SY89874U pinout,Pin out
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