Dual Signal Conditioning Transceiver

TLK1002A is a single-chip dual Signal Conditioning transceiver.
This chip supports data rates from 1.0 Gbps up to 1.3 Gbps. An on-chip Clock generation phase-locked loop (PLL) generates the required half-rate Clock from an externally applied reference Clock This reference Clock equals approximately one tenth of the data rate. It may be off frequency from both received data streams by up to 200 ppm.
Both data paths are implemented identical. The implemented input Buffers provide an input sensitivity of 400 mVp-p differential.
The data paths tolerate up to 0.606 UI total input jitter. Signal retiming is performed by means of phase-locked loop (PLL) circuits. The retimed output signals are fed to VML output Buffers which provide output amplitudes of typical 1600mVp-p differential across the external 2x50 load.
TLK1002A only requires a single 1.8 V supply voltage. Robust design avoids the necessity of special off-chip supply filtering.
Advanced low power CMOS design leads to low power consumption.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
TLK1002ARGET Texas Instruments Dual Signal Conditioning Transceiver 24-VQFN 0 to 70
TLK1002ARGER Texas Instruments Dual Signal Conditioning Transceiver 24-VQFN 0 to 70
TLK1002ARGERG4 Texas Instruments Dual Signal Conditioning Transceiver 24-VQFN 0 to 70
TLK1002ARGETG4 Texas Instruments Dual Signal Conditioning Transceiver 24-VQFN 0 to 70
TLK1002A 's PackagesTLK1002A 's pdf datasheet
TLK1002ARGER QFN
TLK1002ARGERG4 QFN
TLK1002ARGET QFN
TLK1002ARGETG4 QFN




TLK1002A Pinout, Pinouts
TLK1002A pinout,Pin out
This is one package pinout of TLK1002A,If you need more pinouts please download TLK1002A's pdf datasheet.

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