Fixed-Point Digital Signal Processor

The TMS320C64x?DSPs (including the TMS320C6412 device) are the highest-performance fixed-point DSP generation in the TMS320C6000? DSP platform. The TMS320C6412 (C6412) device is based on the second-generation high-performance, advanced VelociTI? very-long-instruction-word (VLIW) architecture (VelociTI.2?) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x? is a code-compatible member of the C6000? DSP platform.
With performance of up to 5760 million instructions per second (MIPS) at a Clock rate of 720 MHz, the C6412 device offers cost-effective solutions to high-performance DSP programming challenges. The C6412 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x? DSP core processor has 64 general-purpose Registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic Logic units (ALUs)?with VelociTI.2? extensions. The VelociTI.2? extensions in the eight functional units include new instructions to accelerate the performance in applications and extend the parallelism of the VelociTI? architecture. The C6412 CAN produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C6412 DSP also has application-specific hardware Logic on-chip memory, and additional on-chip peripherals similar to the other C6000? DSP platform devices.
The C6412 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a- 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory CAN be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port Interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory Interface (EMIFA), which is capable of interfacing to synchronous and asynchronous Memories and peripherals.
The Ethernet media access controller (EMAC) provides an efficient Interface between the C6412 DSP core processor and the network. The C6412 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The C6412 EMAC makes use of a custom Interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP the MDIO module transparently monitors its link state by reading the PHY status Register Link change events are stored in the MDIO module and CAN optionally interrupt the DSP allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO port, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).
The I2C0 port on the TMS320C6412 allows the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral Interface (SPI) mode peripheral devices.
The C6412 has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows? debugger Interface for visibility into source code execution.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
TMS320C6412AGNZ5 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA 0 to 90
TMS320C6412ZDKA500 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA
TMS320C6412ZDK600 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA
TMS320C6412AGDKA5 Texas Instruments Fixed-Point Digital Signal Processor 548-FC/CSP -40 to 105
TMS320C6412ZDK500 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA
TMS320C6412GNZ600 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA
TMS320C6412GNZ500 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA
TMS320C6412AZNZ6 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA 0 to 90
TMS320C6412GNZ720 Texas Instruments Fixed-Point Digital Signal Processor 548-FCBGA
TMS320C6412AGDK6 Texas Instruments Fixed-Point Digital Signal Processor 548-FC/CSP 0 to 90
TMS320C6412 's PackagesTMS320C6412 's pdf datasheet
TMS320C6412AGDK5 FCBGA
TMS320C6412AGDK6 FCBGA
TMS320C6412AGDK7 FCBGA
TMS320C6412AGDKA5 FCBGA
TMS320C6412AGDKA6 FCBGA
TMS320C6412AGNZ5 FCBGA
TMS320C6412AGNZ6 FCBGA
TMS320C6412AGNZ7 FCBGA
TMS320C6412AGNZA5 FCBGA
TMS320C6412AGNZA6 FCBGA
TMS320C6412AZDK5 FCBGA
TMS320C6412AZDK6 FCBGA
TMS320C6412AZDK7 FCBGA
TMS320C6412AZDKA5 FCBGA
TMS320C6412AZNZ5 FCBGA
TMS320C6412AZNZ6 FCBGA
TMS320C6412AZNZ7 FCBGA
TMS320C6412GDK600 FCBGA
TMS320C6412GDK720 FCBGA
TMS320C6412GDKA500 FCBGA
TMS320C6412GNZ500 FCBGA
TMS320C6412GNZ600 FCBGA
TMS320C6412GNZ720 FCBGA
TMS320C6412GNZA500 FCBGA
TMS320C6412ZDK500 FCBGA
TMS320C6412ZDK600 FCBGA
TMS320C6412ZDKA500 FCBGA
TMS320C6412ZNZ500 FCBGA
TMS320C6412ZNZ600 FCBGA
TMX320C6412GDK FCBGA




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