Fixed-Point Digital Signal Processor

The TMS320C64x DSPs (including the TMS320C6414T TMS320C6415T and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000. DSP platform. The TMS320C64x (C64x) device is based on the second-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making these DSPs an excellent choice for Wireless infrastructure applications. The C64x is a code-compatible member of the C6000 DSP platform.
With performance of up to 8000 million instructions per second (MIPS) at a Clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose Registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic Logic units (ALUs)? with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x CAN produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware Logic on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.
The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU Clock divided-by-4 CAN decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU Clock divided-by-2 CAN decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.
The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory CAN be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port Interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory Interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous Memories and peripherals.
The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger Interface for visibility into source code execution.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
TMS320C6415TBGLZ6 Texas Instruments Fixed-Point Digital Signal Processor 532-FCBGA 0 to 90
TMS320C6415TBZLZ7 Texas Instruments Fixed-Point Digital Signal Processor 532-FCBGA 0 to 90
TMS320C6415TBCLZ6 Texas Instruments Fixed-Point Digital Signal Processor 532-FC/CSP 0 to 90
TMS320C6415TBZLZA7 Texas Instruments Fixed-Point Digital Signal Processor 532-FCBGA -40 to 105
TMS320C6415TBZLZA6 Texas Instruments Fixed-Point Digital Signal Processor 532-FCBGA -40 to 105
TMS320C6415TBGLZ8 Texas Instruments Fixed-Point Digital Signal Processor 532-FCBGA 0 to 90
TMS320C6415TBZLZ6 Texas Instruments Fixed-Point Digital Signal Processor 532-FCBGA 0 to 90
TMS320C6415TBGLZA6 Texas Instruments Fixed-Point Digital Signal Processor 532-FCBGA -40 to 105
TMS320C6415TBCLZW7 Texas Instruments Fixed-Point Digital Signal Processor 532-FC/CSP 0 to 90
TMS320C6415TBCLZ7 Texas Instruments Fixed-Point Digital Signal Processor 532-FC/CSP 0 to 90
TMS320C6415T 's PackagesTMS320C6415T 's pdf datasheet
TMS320C6415TBCLZ1
TMS320C6415TBCLZ6
TMS320C6415TBGLZ1 FCBGA
TMS320C6415TBGLZ6 FCBGA
TMS320C6415TBGLZ7 FCBGA
TMS320C6415TBGLZ8 FCBGA
TMS320C6415TBGLZA6 FCBGA
TMS320C6415TBGLZA7 FCBGA
TMS320C6415TBGLZA8 FCBGA
TMS320C6415TBZLZ1 FCBGA
TMS320C6415TBZLZ6 FCBGA
TMS320C6415TBZLZ7 FCBGA
TMS320C6415TBZLZ8 FCBGA
TMS320C6415TBZLZA6 FCBGA
TMS320C6415TBZLZA7 FCBGA
TMS320C6415TBZLZA8 FCBGA
TMS320C6415TGLZ1 FCBGA
TMS320C6415TGLZ6 FCBGA
TMS320C6415TGLZ7 FCBGA
TMS320C6415TGLZ8 FCBGA
TMS320C6415TGLZA6 FCBGA
TMS320C6415TGLZA7 FCBGA
TMS320C6415TGLZA8 FCBGA
TMS320C6415TZLZ1 FCBGA
TMS320C6415TZLZ7 FCBGA
TMS320C6415TZLZ8 FCBGA
TMX320C6415TGLZ FCBGA




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