Digital Media Processor

The TMS320C64x+ DSPs (including the TMS320DM647 TMS320DM648 devices) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The DM647/DM648 devices are based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+ devices are upward code-compatible from previous devices that are part of the C6000 DSP platform. The C64x DSPs support added functionality and have an expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 7200 million instructions per second (MIPS) at a Clock rate of 900 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose Registers of 32-bit word length and eight highly independent functional units?two multipliers for a 32-bit result and six arithmetic Logic units (ALUs). The eight functional units include instructions to accelerate the performance in Video and imaging applications. The DSP core CAN produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).
The DM647/DM648 devices also have application-specific hardware Logic on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM647/DM648 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 256K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 4M-bit (DM648) or 2M-bit (DM647) memory space that is shared between program and data space. L2 memory CAN be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: The DM647/DM648 devices have five configurable 16-bit Video port peripherals (VP0, VP1, VP2, VP3, and VP4). These Video port peripherals provide a glueless Interface to common Video Decoder and encoder devices. The DM647/DM648 Video port peripherals support multiple resolutions and Video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M), a VCXO interpolated control port (VIC); a 1000 Mbps 3-port Switch with a management data input/output (MDIO) module and two SGMII ports (DM648 only); an 1000 Mbps Ethernet media access controller (EMAC) and a management data input/output (MDIO) module (only DM647); a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) bus interface; a multichannel Audio serial port (McASP) with ten serializers; four 64-bit general-purpose Timers each configurable as two independent 32-bit timers; a user-configurable 16-bit or 32-bit host-port Interface (HPI); 32 pins for general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; one UART; and two glueless external memory interfaces: a synchronous and asynchronous external memory Interface (EMIFA) for slower Memories peripherals, and a higher DDR2 SDRAM Interface
The Video port peripherals provide a glueless Interface to common Video Decoder and encoder devices. The Video port peripherals support multiple resolutions and Video standards (e.g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).
The Video port peripherals are configurable and CAN support either Video capture and/or Video Display modes. Each Video port consists of two channels (A and B) with a 5120-byte capture Display Buffer that is splittable between the two channels.
For more details on the Video port peripherals, see the TMS320C64x DSP Video Port VCXO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).
The management data input/output (MDIO) module continuously polls all 32 MDIO addresses to enumerate all PHY devices in the system.
The I2C and VLYNQ ports allow the device to easily control peripheral modules and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The DM647/DM648 devices have a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger Interface for visibility into source code execution.
By Texas Instruments
Part Manufacturer Description Datasheet Samples
TMS320DM648CUTD1 Texas Instruments Digital Media Processor 529-FCBGA -40 to 90
TMS320DM648CUTA6 Texas Instruments Digital Media Processor 529-FCBGA -40 to 105
TMS320DM648ZUT9 Texas Instruments Digital Media Processor 529-FCBGA 0 to 90
TMS320DM648ZUTD7 Texas Instruments Digital Media Processor 529-FCBGA -40 to 90
TMS320DM648ZUT1 Texas Instruments Digital Media Processor 529-FCBGA 0 to 90
TMS320DM648CUT1 Texas Instruments Digital Media Processor 529-FCBGA 0 to 90
TMS320DM648ZUT7 Texas Instruments Digital Media Processor 529-FCBGA 0 to 90
TMS320DM648ZUT9HK Texas Instruments Digital Media Processor 529-FCBGA 0 to 90
TMS320DM648CUTA8 Texas Instruments Digital Media Processor 529-FCBGA -40 to 105
TMS320DM648CUTD9 Texas Instruments Digital Media Processor 529-FCBGA -40 to 90
TMS320DM648 's PackagesTMS320DM648 's pdf datasheet
TMX320DM648ZUT7 FCBGA
TMX320DM648ZUT9 FCBGA




TMS320DM648 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
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