PARALLEL DRIVER

The TMS3473B is a monolithic CMOS integrated circuit designed to drive the parallel image-area Gate (IAG), parallel storage-area Gate (SAG), and antiblooming Gate (ABG) inputs of the Texas Instruments (TI) virtual-phase CCD Image Sensors The TMS3473B Interfaces the CCD Image Sensor to a user-defined Timing generator; it receives TTL-input signals from the Timing generator and outputs level-shifted and slew-rate-adjusted signals to the Image Sensor The TMS3473B allows operation of the CCD Image Sensor in either the interlace or noninterlace mode. When the TMS3473B I/N input is connected to VSS, the interlace mode is selected (see Figure 1); when I/N is connected to VCC, the noninterlace mode is selected (see Figure 2). ABOUT follows ABIN and switches between VABG+ and VABG. IAOUT and SAOUT follow IAIN and SAIN, respectively, and Switch between VCC and VSS. Additionally, ABOUT and IAOUT CAN each be made to output midlevel voltages. DC inputs to ABLVL and IALVL determine the midlevel voltages that CAN be output on ABOUT and IAOUT, respectively. A high-logic level on MIDSEL causes ABOUT to output its midlevel voltage; a low-logic level on MIDSEL causes IAOUT to output its midlevel voltage if the interlace mode is selected. Slew-rate adjustment of IAOUT and ABOUT is accomplished by connecting IASR to VCC and ABSR to VABG+ through external resistors. The larger the resistor values, the longer the rise and fall times are. A low-logic level on PD causes the TMS3473B to power down and all outputs to assume their low levels (IAOUT and SAOUT to VSS, ABOUT to VABG). The TMS3473B is supplied in a 20-pin surface-mount package (DW) and is characterized for operation from 20C to 45C. By Texas Instruments