16/32-Bit RISC Flash Microcontrollers

The TMS470R1VF67A 1) device is a member of the Texas Instruments TMS470R1x family of general-purpose 16/32-bit reduced instruction set computer (RISC) Microcontrollers The VF67A Microcontroller offers high performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF67A utilizes the big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining low costs. The VF67A RISC core architecture offers solutions to these performance and cost demands while maintaining low power consumption.
The VF67A devices contain the following: ARM7TDMI 16/32-Bit RISC CPU TMS470R1x system module (SYS) with 470+ enhancements [including a 16-channel direct-memory access (DMA) controller 215K-byte Flash 32K-byte SRAM Frequency-modulated zero-pin phase-locked loop (FMPLL) Clock module Analog watchdog (AWD) Timer Real-time interrupt (RTI) module Two serial peripheral Interface (SPI) modules One serial Communications Interface (SCI) modules Two high-end CAN controllers (HECC) Class II Serial Interface (C2SIb) Two 10-bit multi-buffered Analog-to-digital converter (MibADC), 16-input channels Multi-buffered serial peripheral Interface (MibSPI) module High-end Timer (HET) controlling 32 I/Os External Clock Prescale (ECP) module Up to 68 I/O pins and 1 input-only pin The functions performed by the 470+ system module (SYS) include: address decoding; memory protection; memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal interrupt sources; device Clock control; and parallel signature analysis (PSA). This data sheet includes devicespecific information such as memory and peripheral select assignment, interrupt priority, and a device memory map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module Reference Guide (literature number SPNU189).
The VF67A memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte, half-word, and word modes.
The Flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented with a 32-bit-wide data bus Interface The Flash operates with a system Clock frequency of up to 24 MHz. When in pipeline mode, the Flash operates with a system Clock frequency of up to 60 MHz. For more detailed information on the Flash see the Flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature number SPNU213). The VF67A device has seven Communication interfaces: a MibSPI, two SPIs, two HECCs, an SCI, and a C2SIb. The SPI provides a convenient method of serial interaction for high-speed Communications between similar shift-register type devices. The SCI is a full-duplex, serial I/O Interface intended for asynchronous Communication between the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The HECC uses a serial, multimaster Communication protocol that efficiently supports distributed real-time control with robust Communication rates of up to1 megabit per second (Mbps). The HECC is ideal for applications operating in harsh environments (e.g., automotive and industrial fields) that require reliable serial Communication or multiplexed wiring. The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length to be shifted into and out of the device at a programmed bit-transfer rate. The C2SIb allows the VF67A to transmit and receive messages on a class II network following an SAE J1850 standard. For more detailed functional information on the SPI, SCI, and HECC peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively). For more detailed functional information on the C2SIb peripheral, see the TMS470R1x Class II Serial Interface B (C2SIb) Reference Guide (literature number SPNU214). For more information on the MibSPI peripheral, see the TMS470R1x Multi-Buffered Serial Peripheral Interface (MibSPI) Reference Guide (literature number SPNU217).
The HET is an advanced intelligent Timer that provides sophisticated Timing functions for real-time applications. The Timer is software-controlled, using a reduced instruction set, with a specialized Timer micromachine and an attached I/O port. The HET CAN be used for compare, capture, or general-purpose I/O. It is especially well suited for applications requiring multiple Sensor information and drive actuators with complex and accurate time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199). The VF67A HET peripheral contains the XOR-share feature. This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
The VF67A device has two 10-bit-resolution sample-and-hold MibADCs. The MibADC channels CAN be converted individually or CAN be grouped by software for sequential conversion sequences. There are three separate groupings, two of which are triggerable by an external event. Each sequence CAN be converted once when triggered or configured for continuous conversion mode. For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-digital Converter (MibADC) Reference Guide (literature number SPNU206).
The frequency-modulated phase-locked loop (FMPLL) Clock module contains a phase-locked loop, a clockmonitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1-8). The function of the FMPLL is to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides ACLK to the system (SYS) module. The SYS module subsequently provides system Clock (SYSCLK), realtime interrupt Clock (RTICLK), CPU Clock (MCLK), and peripheral Interface Clock (ICLK) to all other VF67A device modules. For more detailed functional information on the FMPLL, see the TMS470R1x Frequency- Modulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221).
By Texas Instruments
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