Standard 32k X 8 SramThe U62256 is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
- Read - Standby
- Write - Data Retention
The memory array is based on a
MIXMOS cell.
The circuit is activated by the fal-
ling edge of E. The address and
control inputs open simultaneously.
According to the information of W
and G, the data inputs, or outputs,
are active. In a Read cycle, the
data outputs are activated by the
falling edge of G, afterwards the
data word read will be available at
the outputs DQ0-DQ7. After the
address change, the data outputs
go High-Z until the new information
read is available. The data outputs
have not preferred state. By Unkown
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