Ddr Termination Regulator

The UTC UR5595 is a linear bus termination Regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational Amplifier to provide excellent response to the load transients, and CAN deliver 1.5A continuous current and transient peaks up to 3A in the application as required for DDR-SDRAM termination. By LianShun Electronics Co., Ltd
UR5595 's PackagesUR5595 's pdf datasheet
UR5595-S08-R
UR5595L-S08-R
UR5595-S08-T
UR5595L-S08-T
UR5595-SH2-R
UR5595L-SH2-R
UR5595-SH2-T
UR5595L-SH2-T




UR5595 Pinout, Pinouts
UR5595 pinout,Pin out
This is one package pinout of UR5595,If you need more pinouts please download UR5595's pdf datasheet.

UR5595 Application circuits
UR5595 circuits
This is one application circuit of UR5595,If you need more circuits,please download UR5595's pdf datasheet.


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