Serial Configuration Proms , Inc

The XC1701L XC1701 and XC17512L serial conguration PROMs (SCPs) provide an easy-to-use, cost-effective method for storing Xilinx FPGA conguration bitstreams. When the FPGA is in master serial mode, it generates a conguration Clock that drives the SCP. A short access time after the rising Clock edge, data appears on the SCP DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of Clock pulses to complete the conguration. Once congured, it disables the SCP. When the FPGA is in slave mode, the SCP and the FPGA must both be clocked by an incoming signal. Multiple devices CAN be concatenated by using the CEO output to drive the CE input of the following device. The Clock inputs and the DATA outputs of all SCPs in this chain are interconnected. All devices are compatible and CAN be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foun- dation series development system compiles the FPGA design le into a standard Hex format, which is then trans- ferred to the programmer. By Xilinx Corp.
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