In-system Programmable Configuration Proms , Inc

Xilinx introduces the XC18V00 series XC18V04 XC18V02 XC18V01 XC18V512 of in-system program- mable configuration PROMs (Figure 1). Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-to-use, cost-effec- tive method for re-programming and storing Xilinx FPGA configuration bitstreams. When the FPGA is in Master Serial mode, it generates a configuration Clock that drives the PROM. A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. New data is available a short access time after each ris- ing Clock edge. The FPGA generates the appropriate num- ber of Clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external Clock By Xilinx Corp.
XC18V00 's PackagesXC18V00 's pdf datasheet
XC18V04VQ44C
XC18V02VQ44C
XC18V01VQ44C
XC18V512VQ44C
XC18V04PC44C
XC18V02PC44C
XC18V01PC20C
XC18V512PC20C
XC18V04
XC18V02
XC18V01
XC18V512
XC18V01SO20C
XC18V512SO20C




XC18V00 Pinout, Pinouts
XC18V00 pinout,Pin out
This is one package pinout of XC18V00,If you need more pinouts please download XC18V00's pdf datasheet.

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