XC2C512 CoolRunner-II CPLD

The CoolRunner-II 512-macrocell device XC2C512 is designed for both high performance and low power applications. This lends power savings to high-end Communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reli- ability is improved This device consists of thirty two Function Blocks inter-con- nected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these Registers CAN be globally reset or preset and configured as a D or T Flip-Flop or as a D latch. There are also multiple Clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to stor- ing macrocell output states, the macrocell Registers may be configured as "direct input" Registers to store signals directly from input pins. By Xilinx Corp.
XC2C512 's PackagesXC2C512 's pdf datasheet
XC2C512-7PQ208C
XC2C512-10PQ208C
XC2C512-7FT256C
XC2C512-7FT256I
XC2C512-10FT256C
XC2C512-7FG324C
XC2C512-10FG324C
XC2C512-7PQG208C
XC2C512-10PQG208C
XC2C512-7FTG256C
XC2C512-7FTG256I
XC2C512-10FTG256C
XC2C512-7FGG324C
XC2C512-10FGG324C
XC2C512-10PQ208I
XC2C512-10FT256I
XC2C512-10FG324I
XC2C512-10PQG208I
XC2C512-10FTG256I
XC2C512-10FGG324I




XC2C512 Pinout, Pinouts
XC2C512 pinout,Pin out
This is one package pinout of XC2C512,If you need more pinouts please download XC2C512's pdf datasheet.

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