Virtex-5 Family Overview

The Virtex-5 family provides the newest most powerful features in the FPGA market. Using the second generation ASMBL (Advanced Silicon Modular Block) column-based architecture, the Virtex-5 family contains four distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced Logic designs. In addition to the most advanced, high-performance Logic fabric, Virtex-5 FPGAs contain many hard-IP system level blocks, including powerful 36-Kbit block RAM FIFOs second generation 25 x 18 DSP slices, SelectIO technology with built-in digitally- controlled impedance, ChipSync source-synchronous Interface blocks, system monitor functionality, enhanced Clock management tiles with integrated DCM (Digital Clock Managers) and phase-locked-loop (PLL) Clock Generators and advanced configuration options. Additional platform dependant features include power-optimized high-speed serial transceiver blocks for enhanced serial connectivity, PCI Express compliant integrated Endpoint blocks, tri-mode Ethernet MACs (Media Access Controllers), and high-performance PowerPC 440 Microprocessor embedded blocks. These features allow advanced Logic designers to build the highest levels of performance and functionality into their FPGA-based systems. Built on a 65-nm state-of-the-art copper process technology, Virtex-5 FPGAs are a programmable alternative to custom ASIC technology. Most advanced system designs require the programmable strength of FPGAs Virtex-5 FPGAs offer the best solution for addressing the needs of high-performance Logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented Logic DSP hard/soft Microprocessor and connectivity capabilities. The Virtex-5 LXT, SXT, and FXT platforms include advanced high-speed serial connectivity and link/transaction layer capability. By Xilinx Corp.