Xc9500xv Family High-performance Cpld , Inc

The XC9500XV family is a 2.5V CPLD family targeted for high-performance, low-voltage applications in leading-edge Communications and computing systems, where high device reliability and low power dissipation is important. Each XC9500XV device supports in-system programming (ISP) and the full IEEE 1149.1 (JTAG) boundary-scan, allowing superior debug and design iteration capability for small form-factor packages. The XC9500XV family is designed to work closely with the Xilinx Spartan-XL and Vir- tex FPGA families, allowing system designers to partition Logic optimally between fast Interface circuitry and high-den- sity general purpose Logic As shown in Table 1, Logic den- sity of the XC9500XV devices ranges from 800 to 6400 usable Gates with 36 to 288 Registers respectively. Multiple package options and associated I/O capacity are shown in Table 2. The XC9500XV family members are fully pin-com- patible, allowing easy design migration across multiple den- sity options in a given package footprint. The XC9500XV architectural features address the require- ments of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system program- ming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operat- ing life. By Xilinx Corp.
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