64 Macrocell Cpld With Enhanced Clocking , Inc

The XCR3064A CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner CPLDs from Xilinx. These devices combine high speed and zero power in a 64 macrocell CPLD With the FZP design tech- nique, the XCR3064A offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 A at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense Amplifier methods for implementing product terms (a tech- nique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS Gates the dynamic power is also substantially lower than any competing CPLD These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the pat- ented full CMOS FZP design technique. By Xilinx Corp.
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XCR3064A Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
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