32 Macrocell Cpld , Inc

The XCR5032 CPLD (Complex Programmable Logic Device) is the first in a family of CoolRunner CPLDs from Xilinx. These devices combine high speed and zero power in a 32 macrocell CPLD With the FZP design technique, the XCR5032 offers true pin-to-pin speeds of 6 ns, while simultaneously delivering power that is less than 75 A at standby without the need for "turbo bits" or other power down schemes. By replacing conventional sense Amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cas- caded chain of pure CMOS Gates the dynamic power is also substantially lower than any competing CPLD These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 3V applications, Xilinx also offers the high speed XCR3032 CPLD that offers these fea- tures in a full 3V implementation. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible Logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each Logic block provides a fast 6 ns PAL path with five ded- icated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 prod- uct terms to a fully programmable OR array that CAN allo- cate the PLA product terms to any output in the Logic block. This combination allows Logic to be allocated efficiently throughout the Logic block and supports as many as 37 product terms on an output. The speed with which Logic is allocated from the PLA array to an output is only 2 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 8 ns from any pin to any other pin. In addition, Logic that is common to multiple out- puts CAN be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. By Xilinx Corp.