64 Macrocell Cpld With Enhanced Clocking , Inc

The XCR5064C CPLD (Complex Programmable Logic Device) is the second in a family of CoolRunner CPLDs from Xilinx Semiconductors. These devices combine high speed and zero power in a 64 macrocell CPLD With the FZP design technique, the XCR5064C offers true pin-to-pin speeds of 7.5 ns, while simultaneously delivering power that is less than 100 A at standby without the need for `turbo bits' or other power down schemes. By replacing conventional sense Amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS Gates the dynamic power is also substantially lower than any competing CPLDz. These devices are the first TotalC- MOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. The Xilinx FZP CPLDs utilize the patented XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible Logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each Logic block provides a fast 7.5 ns PAL path with five dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that CAN allocate the PLA product terms to any output in the Logic block. This combination allows Logic to be allocated effi- ciently throughout the Logic block and supports as many as 37 product terms on an output. The speed with which Logic is allocated from the PLA array to an output is only 2.0 ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.5 ns from any pin to any other pin. In addition, Logic that is common to multiple out- puts CAN be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR5084C CPLDs are supported by industry stan- dard CAE tools (Cadence/OrCAD, Exemplar Logic Mentor, Synopsys, Synario, Viewlogic, and Synplicity), using text (ABEL, VHDL, Verilog) and/or schematic entry. Design ver- ification uses industry standard simulators for functional and Timing simulation. Development is supported on per- sonal computer, Sparc, and HP platforms. Device fitting uses Xilinx developed tools including WebFITTER. By Xilinx Corp.
XCR5064C 's PackagesXCR5064C 's pdf datasheet



XCR5064C Pinout, Pinouts
XCR5064C pinout,Pin out
This is one package pinout of XCR5064C,If you need more pinouts please download XCR5064C's pdf datasheet.

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