X1 PCI Express PHY, Compliant With The PCI Express Base Specification Revision 1.1

The XIO1100 is a PCI Express? PHY that is compliant with PCI Express Base Specification Revision 1.1 and that Interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified version of the Interface described in PHY Interface for the PCI Express? Architecture (also known as PIPE interface) by Intel Corporation. This modified version of the PIPE Interface is referred to as a TI-PIPE Interface throughout this data manual.
The TI-PIPE Interface is a pin-configurable Interface that CAN be configured as either a 16-bit or an 8-bit Interface The 16-bit TI-PIPE Interface is a 125 MHz 16-bit parallel Interface with a 16-bit output bus (RXDATA) that is clocked by the RXCLK output Clock and a 16-bit input bus (TXDATA) that is clocked by the TXCLK input Clock Both buses are clocked using Single Data Rate (SDR) clocking in which the data transitions are on the rising edge of the associated Clock The 8-bit TI-PIPE Interface is a 250 MHz 8-bit parallel Interface with an 8-bit output bus (RXDATA) that is clocked by the RXCLK output Clock and an 8-bit input bus (TXDATA) that is clocked by the TXCLK input Clock Both buses are clocked using Double Data Rate (DDR) clocking in which the data transitions are on both the rising edge and the falling edge of the Clock
The XIO1100 PHY Interfaces to a 2.5 Gbps PCI Express serial link with a transmit differential pair (TXP and TXN) and a receive differential pair (RXP and RXN). Incoming data at the XIO1100 PHY receive differential pair (RXP and RXN) is forwarded to the MAC on the RXDATA output bus. Data received from the MAC on the TXDATA input bus is forwarded to the XIO1100 PHY transfer differential pair (TXP and TXN).
The XIO1100 is also responsible for handling the 8B/10B encoding/decoding and scrambling/unscrambling of the outgoing data. In addition, XIO1100 CAN recover/interpolate the Clock on the receiver side based on the transitions guaranteed by the use of the 8B/10B mechanism and supply this to the receive side of the data link layer Logic
In addition to the TI-PIPE Interface the XIO1100 has some TI-proprietary side-band signals that some customers may wish to use to take advantage of additional XIO1100 low-power state features (for example, disabling the PLL during the L1 power state).
By Texas Instruments
Part Manufacturer Description Datasheet Samples
XIO1100GGB Texas Instruments x1 PCI Express PHY 100-BGA MICROSTAR 0 to 70
XIO1100ZGB Texas Instruments x1 PCI Express PHY 100-BGA MICROSTAR 0 to 70
XIO1100ZGBR Texas Instruments x1 PCI Express PHY 100-BGA MICROSTAR 0 to 70
CYCLONE-IITM-PCI-EXPRESS-DEVELOPMENT-KIT Texas Instruments PCI Express x1 Development kit based on Cyclone II? and XIO1100
XIO1100 's PackagesXIO1100 's pdf datasheet
XIO1100GGB BGA




XIO1100 Pinout will be updated soon..., now you can download the pdf datasheet to check the pinouts !
XIO1100 Application circuits
XIO1100 circuits
This is one application circuit of XIO1100,If you need more circuits,please download XIO1100's pdf datasheet.


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