Stratum 3 Redundant System Clock Synchronizer For T1/E1/SDH, Advanced TCA And H.110

The ZL30105 is a high-performance DPLL (digital phase-locked loop) designed for synchronization and Timing control of redundant system Clocks requiring Stratum 3 and SDH Timing specifications. The ZL30105 generates SBI, ST-BUS and other TDM Clock and framing signals that are phase locked to one of three network references. It helps ensure system reliability by monitoring its references for frequency accuracy and stability and by maintaining tight phase alignment between redundant primary and secondary system Clocks even in the presence of high network jitter. The ZL30105 is intended to be the central Timing and synchronization resource for network equipment that complies with ITU-T, Telcordia, ETSI and ANSI network specifications.
By Zarlink Semiconductor
ZL30105 's PackagesZL30105 's pdf datasheet
ZL30105QDG PDIP
ZL30105QDG1 PDIP




ZL30105 Pinout, Pinouts
ZL30105 pinout,Pin out
This is one package pinout of ZL30105,If you need more pinouts please download ZL30105's pdf datasheet.

ZL30105 circuits will be updated soon..., now you can download the pdf datasheet to check the circuits!

Related Electronics Part Number

Related Keywords:

ZL30105 Pb-Free ZL30105 Cross Reference ZL30105 Schematic ZL30105 Distributor
ZL30105 Application Notes ZL30105 RoHS ZL30105 Circuits ZL30105 footprint