SONET/SDH Clock Multiplier PLL

SONET SDH Clock Multiplier PLL ,The ZL30416 is an Analog Phase-Locked Loop (APLL) designed to provide jitter attenuation and rate conversion for SDH (Synchronous Digital Hierarchy) and SONET (Synchronous Optical Network) networking equipment. The ZL30416 generates low jitter output Clocks suitable for Telcordia GR-253- CORE OC-192, OC-48, OC-12, OC-3, and OC-1 and ITU-T G.813 STM-64, STM-16, STM-4 and STM-1 applications. The ZL30416 accepts a CMOS compatible reference at 19.44 MHz or a differential LVDs LVPECL or CML reference at 19.44 or 77.76 MHz and generates a differential LVPECL output Clock selectable to 19.44, 38.88, 77.76, 155.52 or 622.08 MHz and a single- ended CMOS Clock at 19.44 MHz. The ZL30416 provides a lock indication. By Zarlink Semiconductor
ZL30416 's PackagesZL30416 's pdf datasheet

ZL30416 Pinout, Pinouts
ZL30416 pinout,Pin out
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